The testing of integrated circuits can occur throughout the life of a device. An integrated circuit may be tested in die form, while still part of a wafer, in packaged form at the “back” end of a manufacturing process, and/or after the device has been incorporated into a system (“in system” testing).
In order to reduce overall integrated circuit (i.e., chip) test costs, some chips are fabricated with built-in self-test (BIST) circuitry. Such circuitry is considered “built-in” as it is included on the chip itself or as part of a package containing the chip. This can allow for internally generated test patterns to be applied to a portion of the chip. BIST capabilities can increase the speed at which a device is tested, as an integrated circuit can typically operate at a faster speed than a tester (i.e., automatic test equipment, ATE).
In memory devices, including content addressable memory (CAM) devices, it is desirable to self-test each storage location to determine whether or not it is operating properly. CAM devices can have large numbers of entries, each of which includes a number of CAM cells that are typically more complex than other types of memory cells, as they can include built-in compare circuitry. Thus, the ability to test such addressable locations can significantly reduce overall manufacturing costs.
To better understand the various features of the embodiments disclosed below, conventional BIST approaches will now be described in more detail.
A conventional BIST arrangement is shown In FIG. 4 and designated by the general reference character 400. A BIST arrangement 400 can include a tested section 402 that can provide some predetermined function and a BIST section 404 that can test various functions of the tested section 402. In the particular example of FIG. 4, a BIST arrangement 400 shows a tested section 402 that includes a content addressable memory (CAM) array 405, control logic 406, and a test MUX 408. In a non-test mode, test MUX 408 can couple input data by way of input I/P to control logic 406. In response to such inputs, control logic 406 can execute predetermined functions on one or more CAM arrays 405, resulting output data can be output from control logic 406 at output O/P.
A BIST section 404 can include a BIST generator 410, a BIST checker 412, and can also utilize a test MUX 408. In a test mode, a BIST generator 410 can generate address values and corresponding data values for application to CAM array 405. Test output data generated in response to such tests can be provided to BIST checker 412. Within BIST checker 412, a BIST result checker 414 can determine if a tested CAM entry is defective or not. Addresses of defective CAM entries can be stored in fault first-in-first-out (FIFO) circuit 416. These fault address values can be output as part of a BIST operation to indicate where faults have been detected within CAM array 405. Such information can aid in implementing redundancy or other techniques in order to increase yields of such devices.
FIG. 5 is a block diagram representation of a conventional BIST generator and BIST checker, like that shown as 410 and 412, respectively, in FIG. 4. FIG. 5 shows a conventional BIST checker 510 that includes an algorithm selector 520, an address generator 522, and data generator 524. An algorithm selector 520 can control how addresses and data are generated by address generator 522 and data generator 524 when testing a device. Conventionally, in a given test, an address generator 522 can generate addresses starting with a lowest address and ending with a highest address, or run particular test patterns that cover all locations within such addresses.
Conventionally, a highest and lowest address can be “hard coded” values. That is, these values can be inherent in the circuit design and not programmable or otherwise changeable after the device has been manufactured. For example, in a 64K device (or 64K section of a device) such addresses (or less significant bits of an address) can be 0000(hex) and FFFF(hex).
Referring still to FIG. 5, a BIST checker 512 is shown to include a fault FIFO 516. A fault FIFO 516 can store addresses of locations within a CAM array that are determined to be faulty. Such addresses can be reported (i.e., output in some form) in a BIST operation. The number of storage locations within a fault FIFO is finite and preferably small in order to not consume valuable circuit area.
A drawback to a conventional arrangement like that of FIGS. 4 and 5 is shown in FIG. 6. FIG. 6 is a diagrammatic representation of the address space of a CAM device. The CAM device 600 includes a number of addresses ranging from 0000(hex) to FFFF(hex). CAM entries determined to be defective are indicated by solid rectangles. The example of FIG. 6 assumes that a fault FIFO has a depth of three (three storage locations).
FIG. 6 illustrates a result when the number of faulty addresses exceeds a fault FIFO depth. In such a case, a tested address range 602 starts at address 0000 and ends at address FFFF. Starting at address 0000, a fault FIFO can store (and hence report) three failing addresses 604. However, because a FIFO is filled after that point, a fourth and all subsequent failing addresses will be “non-detected faults” 606. Thus, in order to acquire all faulty locations, a BIST operation must be abandoned or supplemented by a full array test on automatic test equipment (ATE). This can increase test time and cost.